Error Correction Code "Viterbi Decoder"
Soft decision decoding / hard decision decoding, error correction codes that support both.
The "Viterbi Decoder" is an FPGA IP core that corresponds to the Viterbi decoding of convolutional codes, which are widely used as representative error correction coding schemes. It supports both soft decision decoding and hard decision decoding. It is compatible with constraint length 7 (171 oct, 133 oct) convolutional codes, which are standard in many communication standards including IEEE802.11a. It can be applied to various applications. 【Features】 ■ Achieves a maximum line speed of approximately 110 Mbps, adaptable to the IEEE802.11a standard ■ Built-in depuncturing function ■ Supports coding rates of 1/2, 2/3, 3/4, 4/5, 5/6, 6/7, and 7/8 ■ Implements a speed conversion block corresponding to the coding rate ■ Configuration that does not use memory blocks (EAB) ■ Allows setting of traceback length via parameters ■ Configurable soft decision bit width *For more details, please refer to the PDF document or feel free to contact us.
- 企業：テクノクリエート
- 価格：Other
